The present invention relates generally to the field of circuit design synthesis, and more particularly to circuit design synthesis through hardware description language.
For the design of digital circuits on the scale of VLSI (Very Large Scale Integration) technology, designers often employ computer-aided techniques. Standard languages known as Hardware Description Languages (HDL""s) have been developed to describe digital circuits to aid in the design and simulation of complex digital circuits. Several hardware description languages, such as VHDL and Verilog, have evolved as industry standards. VHDL and Verilog are general purpose hardware description languages that allow definition of a hardware model at the gate level, the register transfer level (RTL), or the behavioral level using abstract data types. As device technology continues to advance, various product design tools have been developed to adapt HDLs for use with newer devices and design styles.
In designing circuits using HDL compilers, designers first describe circuit elements in HDL source code and then compile the source code to produce synthesized RTL netlists. The RTL netlists correspond to schematic representations of the circuit elements. The circuits containing the synthesized circuit elements are often optimized to improve timing relationships and eliminate unnecessary or redundant logic elements. Such optimization typically involves substituting different gate types or combining and eliminating gates in the circuit, and often results in re-ordering the hierarchies and relationships between the original RTL objects and the underlying source code that produced the RTL objects.
Since object generation can happen during many different phases of synthesis, naming the objects in a consistent way is a challenge. Typical present circuit synthesis systems use a simple global counter mechanism and a fixed prefix to generate object names. Such implementation is inflexible because the generated names, such as instance names and net names, are not repeatable from one synthesis run to the next. This causes problems with repeatability, analysis, debug, incremental design, floorplanning and partitioning.
The present invention discloses methods and apparatuses that determine object names by analyzing the local context and using that information to generate repeatable names.
In one embodiment, a circuit element is described in text representation in a HDL source code file. The text representation is provided to a synthesis compiler for compilation. The text representation contains multiple expressions describing the logic circuits. During a synthesis compilation, object names are selected for each expression in the text representation. The object names are derived from local counters and from the expressions depending on the context of the expressions such that a revision of one section of the source HDL text only affects the object names of the expressions local to the revised section. The object names of other sections of the source HDL text are not affected and remain the same.
The present invention provides computer systems which are capable of performing methods of the invention, and the invention also provides computer readable material which, when executed on a digital processing system, such as a computer system, causes the system to execute one or more of the methods of the invention.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.